// ******************************************************************************
// Copyright     :  Copyright (C) 2019, Hisilicon Technologies Co. Ltd.
// File name     :  SD5860_sd5860_addr_define.h
// Project line  :
// Department    :
// Author        :  xxx
// Version       :  1.0
// Date          :
// Description   :  xxx
// Others        :  Generated automatically by nManager V5.1
// History       :  xxx 2019/09/18 10:05:20 Create file
// ******************************************************************************
#ifndef HI1823_CSR_TILE_ADDR_DEFINE_H
#define HI1823_CSR_TILE_ADDR_DEFINE_H
#define SD5860_SD5860_ADDR_DEFINE_H

/* tile_l2i_csr Base address of Module's Register */
#define CSR_TILE_L2I_CSR_BASE (0x100)

/* **************************************************************************** */
/*                      tile_l2i_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_TILE_L2I_CSR_TILE_L2I_VERSION_REG (CSR_TILE_L2I_CSR_BASE + 0x0) /* Version Log register */
#define CSR_TILE_L2I_CSR_TILE_L2I_PRELOAD_EN_REG \
    (CSR_TILE_L2I_CSR_BASE + 0x4) /* l2i preload enable control.Wiret 1 to start preload */
#define CSR_TILE_L2I_CSR_TILE_L2I_PRELOAD_START_ADDR_REG (CSR_TILE_L2I_CSR_BASE + 0x8) /* l2i preload start address */
#define CSR_TILE_L2I_CSR_TILE_L2I_PRELOAD_CACHELINE_NUM_M1_REG \
    (CSR_TILE_L2I_CSR_BASE + 0xC) /* the cache line number minus 1 .The leagle configuration is 0x0~0x7ff */
#define CSR_TILE_L2I_CSR_TILE_L2I_FETCH_API_CFG_REG (CSR_TILE_L2I_CSR_BASE + 0x10) /* L2I fetch API field. */
#define CSR_TILE_L2I_CSR_TILE_L2I_IMR_CFG_REG (CSR_TILE_L2I_CSR_BASE + 0x14)       /* IMR configuration */
#define CSR_TILE_L2I_CSR_TILE_L2I_TIMEOUT_THD_REG (CSR_TILE_L2I_CSR_BASE + 0x18)   /* timeout threshold configuration */
#define CSR_TILE_L2I_CSR_TILE_L2I_INT_0_VECTOR_REG (CSR_TILE_L2I_CSR_BASE + 0x1C)
#define CSR_TILE_L2I_CSR_TILE_L2I_INT_0_REG (CSR_TILE_L2I_CSR_BASE + 0x20)
#define CSR_TILE_L2I_CSR_TILE_L2I_INT_0_MASK_REG (CSR_TILE_L2I_CSR_BASE + 0x24)
#define CSR_TILE_L2I_CSR_TILE_L2I_TIMEOUT_ERR_QCM0_REG \
    (CSR_TILE_L2I_CSR_BASE + 0x28) /* L2I fetch instruction timeout for QCM0 */
#define CSR_TILE_L2I_CSR_TILE_L2I_TIMEOUT_ERR_QCM0_MASK_REG (CSR_TILE_L2I_CSR_BASE + 0x2C)
#define CSR_TILE_L2I_CSR_TILE_L2I_TIMEOUT_ERR_QCM1_REG \
    (CSR_TILE_L2I_CSR_BASE + 0x30) /* L2I fetch instruction timeout for QCM1 */
#define CSR_TILE_L2I_CSR_TILE_L2I_TIMEOUT_ERR_QCM1_MASK_REG (CSR_TILE_L2I_CSR_BASE + 0x34)
#define CSR_TILE_L2I_CSR_TILE_L2I_TIMEOUT_ERR_QCM2_REG \
    (CSR_TILE_L2I_CSR_BASE + 0x38) /* L2I fetch instruction timeout for QCM2 */
#define CSR_TILE_L2I_CSR_TILE_L2I_TIMEOUT_ERR_QCM2_MASK_REG (CSR_TILE_L2I_CSR_BASE + 0x3C)
#define CSR_TILE_L2I_CSR_TILE_L2I_TIMEOUT_ERR_QCM3_REG \
    (CSR_TILE_L2I_CSR_BASE + 0x40) /* L2I fetch instruction timeout for QCM3 */
#define CSR_TILE_L2I_CSR_TILE_L2I_TIMEOUT_ERR_QCM3_MASK_REG (CSR_TILE_L2I_CSR_BASE + 0x44)
#define CSR_TILE_L2I_CSR_TILE_L2I_TIMEOUT_ERR_QCM4_REG \
    (CSR_TILE_L2I_CSR_BASE + 0x48) /* L2I fetch instruction timeout for QCM4 */
#define CSR_TILE_L2I_CSR_TILE_L2I_TIMEOUT_ERR_QCM4_MASK_REG (CSR_TILE_L2I_CSR_BASE + 0x4C)
#define CSR_TILE_L2I_CSR_TILE_L2I_TIMEOUT_ERR_QCM5_REG \
    (CSR_TILE_L2I_CSR_BASE + 0x50) /* L2I fetch instruction timeout for QCM5 */
#define CSR_TILE_L2I_CSR_TILE_L2I_TIMEOUT_ERR_QCM5_MASK_REG (CSR_TILE_L2I_CSR_BASE + 0x54)
#define CSR_TILE_L2I_CSR_TILE_L2I_MEM_1BIT_ECC_ERR_REG (CSR_TILE_L2I_CSR_BASE + 0x58) /* L2I memory 1 bit ecc error */
#define CSR_TILE_L2I_CSR_TILE_L2I_MEM_2BIT_ECC_ERR_REG (CSR_TILE_L2I_CSR_BASE + 0x5C) /* L2I memory 2 bit ecc error */
#define CSR_TILE_L2I_CSR_TILE_L2I_PERF_CNT_REG (CSR_TILE_L2I_CSR_BASE + 0x60)         /* counter for all L2I miss */
#define CSR_TILE_L2I_CSR_TILE_L2I_INIT_EN_REG (CSR_TILE_L2I_CSR_BASE + 0x64) /* initialization the L2I memory bank. */
#define CSR_TILE_L2I_CSR_TILE_L2I_DONE_HIST_REG (CSR_TILE_L2I_CSR_BASE + 0x68)
#define CSR_TILE_L2I_CSR_TILE_L2I_SP_RAM_TMOD_REG (CSR_TILE_L2I_CSR_BASE + 0x6C) /* ARM memory speed control */
#define CSR_TILE_L2I_CSR_TILE_L2I_CLR_V_FLAG_REG \
    (CSR_TILE_L2I_CSR_BASE + 0x70) /* control register to clear the v flag in L2I, after l2i time out */
#define CSR_TILE_L2I_CSR_TILE_L2I_MOD_REG (CSR_TILE_L2I_CSR_BASE + 0x74)           /* mode configuration for L2I */
#define CSR_TILE_L2I_CSR_L2I_INDRECT_CTRL_REG (CSR_TILE_L2I_CSR_BASE + 0x78)       /* L2I间接寻址控制寄存器 */
#define CSR_TILE_L2I_CSR_L2I_INDRECT_TIMEOUT_REG (CSR_TILE_L2I_CSR_BASE + 0x7C)    /* L2I间接寻址TIMEOUT配置寄存器 */
#define CSR_TILE_L2I_CSR_L2I_INDRECT_DATA_REG (CSR_TILE_L2I_CSR_BASE + 0x80)       /* L2I间接寻址数据寄存器 */
#define CSR_TILE_L2I_CSR_TILE_L2I_ECC_ERR_INJ_0_REG (CSR_TILE_L2I_CSR_BASE + 0x84) /* L2I Bank0/1 ECC错误插入寄存器 */
#define CSR_TILE_L2I_CSR_TILE_L2I_ECC_ERR_INJ_1_REG (CSR_TILE_L2I_CSR_BASE + 0x88) /* L2I Bank2/3 ECC错误插入寄存器 */
#define CSR_TILE_L2I_CSR_TILE_L2I_MISS_ADDR_REG (CSR_TILE_L2I_CSR_BASE + 0x8C)     /* 抓取L2I miss的指令地址高27bit */
#define CSR_TILE_L2I_CSR_TILE_L2I_IMR_EXT_REG (CSR_TILE_L2I_CSR_BASE + 0x90)       /* IMR configuration 1 */

/* tile_ppe_csr Base address of Module's Register */
#define CSR_TILE_PPE_CSR_BASE (0x300)

/* **************************************************************************** */
/*                      tile_ppe_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_TILE_PPE_CSR_PPE_VERSION_REG (CSR_TILE_PPE_CSR_BASE + 0x0)          /* Version Log register for PPE */
#define CSR_TILE_PPE_CSR_PPE_CFG_REG (CSR_TILE_PPE_CSR_BASE + 0x4)              /* PPE configure register */
#define CSR_TILE_PPE_CSR_PPE_TIMEOUT_CFG_REG (CSR_TILE_PPE_CSR_BASE + 0x8)      /* PPE configure register */
#define CSR_TILE_PPE_CSR_PPE_MEM_CFG_REG (CSR_TILE_PPE_CSR_BASE + 0xC)          /* PPE Memory configure register */
#define CSR_TILE_PPE_CSR_PPE_INT_VECTOR_REG (CSR_TILE_PPE_CSR_BASE + 0x10)      /* PPE interrupt vector register */
#define CSR_TILE_PPE_CSR_PPE_INT_REG (CSR_TILE_PPE_CSR_BASE + 0x14)             /* PPE interrupt register */
#define CSR_TILE_PPE_CSR_PPE_INT_MASK_REG (CSR_TILE_PPE_CSR_BASE + 0x18)        /* PPE interrupt mask register */
#define CSR_TILE_PPE_CSR_PPE_MEM_ERR_REG (CSR_TILE_PPE_CSR_BASE + 0x1C)         /* PPE MEM error register */
#define CSR_TILE_PPE_CSR_PPE_MEM_ERR_MASK_REG (CSR_TILE_PPE_CSR_BASE + 0x20)    /* PPE MEM error mask register */
#define CSR_TILE_PPE_CSR_PPE_MEM_ERR_INFO_REG (CSR_TILE_PPE_CSR_BASE + 0x24)    /* PPE MEM error info register */
#define CSR_TILE_PPE_CSR_PPE_TIMEOUT_ERR_REG (CSR_TILE_PPE_CSR_BASE + 0x28)     /* PPE timeout error register */
#define CSR_TILE_PPE_CSR_PPE_INDRECT_CTRL_REG (CSR_TILE_PPE_CSR_BASE + 0x2C)    /* indirect access address registers */
#define CSR_TILE_PPE_CSR_PPE_INDRECT_TIMEOUT_REG (CSR_TILE_PPE_CSR_BASE + 0x30) /* memory access timeout configure */
#define CSR_TILE_PPE_CSR_PPE_INDRECT_DATA_0_REG (CSR_TILE_PPE_CSR_BASE + 0x34)  /* indirect access data registers 0 */
#define CSR_TILE_PPE_CSR_PPE_INDRECT_DATA_1_REG (CSR_TILE_PPE_CSR_BASE + 0x38)  /* indirect access data registers 1 */
#define CSR_TILE_PPE_CSR_PPE_INDRECT_DATA_2_REG (CSR_TILE_PPE_CSR_BASE + 0x3C)  /* indirect access data registers 2 */
#define CSR_TILE_PPE_CSR_PPE_INDRECT_DATA_3_REG (CSR_TILE_PPE_CSR_BASE + 0x40)  /* indirect access data registers 3 */
#define CSR_TILE_PPE_CSR_PPE_INDRECT_DATA_4_REG (CSR_TILE_PPE_CSR_BASE + 0x44)  /* indirect access data registers 4 */
#define CSR_TILE_PPE_CSR_PPE_INDRECT_DATA_5_REG (CSR_TILE_PPE_CSR_BASE + 0x48)  /* indirect access data registers 5 */
#define CSR_TILE_PPE_CSR_PPE_CNT_CFG_REG (CSR_TILE_PPE_CSR_BASE + 0x4C)         /* PPE counter configure register */
#define CSR_TILE_PPE_CSR_PPE_CNT0_REG (CSR_TILE_PPE_CSR_BASE + 0x50)            /* PPE counter 0 register */
#define CSR_TILE_PPE_CSR_PPE_CNT1_REG (CSR_TILE_PPE_CSR_BASE + 0x54)            /* PPE counter 1 register */
#define CSR_TILE_PPE_CSR_PPE_CNT2_REG (CSR_TILE_PPE_CSR_BASE + 0x58)            /* PPE counter 2 register */
#define CSR_TILE_PPE_CSR_PPE_CNT3_REG (CSR_TILE_PPE_CSR_BASE + 0x5C)            /* PPE counter 3 register */
#define CSR_TILE_PPE_CSR_PPE_STAT_CTP_REG (CSR_TILE_PPE_CSR_BASE + 0x60)        /* PPE profiling register 0 */
#define CSR_TILE_PPE_CSR_PPE_PC_CTP_REG (CSR_TILE_PPE_CSR_BASE + 0x64)          /* PPE profiling register 1 */
#define CSR_TILE_PPE_CSR_PPE_PW_MW_OUT_OF_RANGE_ERR_REG \
    (CSR_TILE_PPE_CSR_BASE + 0x68) /* PPE PW MW Out of range error register */
#define CSR_TILE_PPE_CSR_PPE_SE_INS_EXE_CNT_REG (CSR_TILE_PPE_CSR_BASE + 0x6C) /* PPE counter register */
#define CSR_TILE_PPE_CSR_PPE_BE_INS_EXE_CNT_REG (CSR_TILE_PPE_CSR_BASE + 0x70) /* PPE counter register */
#define CSR_TILE_PPE_CSR_PPE_EE_INS_EXE_CNT_REG (CSR_TILE_PPE_CSR_BASE + 0x74) /* PPE counter  register */
#define CSR_TILE_PPE_CSR_PPE_ERR_NUM_REG \
    (CSR_TILE_PPE_CSR_BASE + 0x78) /* The number of error api received in SPC I/F */
#define CSR_TILE_PPE_CSR_PPE_STAT_CTP2_REG (CSR_TILE_PPE_CSR_BASE + 0x7C)        /* PPE profiling register 1 */
#define CSR_TILE_PPE_CSR_PPE_PROG_ENT_ADDR_0_REG (CSR_TILE_PPE_CSR_BASE + 0x80)  /* PPE程序入口统计地址配置 */
#define CSR_TILE_PPE_CSR_PPE_PROG_ENT_ADDR_1_REG (CSR_TILE_PPE_CSR_BASE + 0x84)  /* PPE程序入口统计地址配置 */
#define CSR_TILE_PPE_CSR_PPE_PROG_EXIT_ADDR_0_REG (CSR_TILE_PPE_CSR_BASE + 0x88) /* PPE程序出口统计地址配置 */
#define CSR_TILE_PPE_CSR_PPE_PROG_EXIT_ADDR_1_REG (CSR_TILE_PPE_CSR_BASE + 0x8C) /* PPE程序出口统计地址配置 */
#define CSR_TILE_PPE_CSR_ENT_NUM_0_REG (CSR_TILE_PPE_CSR_BASE + 0x90)            /* 匹配对应PPE程序入口地址的请求次数 */
#define CSR_TILE_PPE_CSR_ENT_NUM_1_REG (CSR_TILE_PPE_CSR_BASE + 0x94)            /* 匹配对应PPE程序入口地址的请求次数 */
#define CSR_TILE_PPE_CSR_ENT_NUM_2_REG (CSR_TILE_PPE_CSR_BASE + 0x98)            /* 匹配对应PPE程序入口地址的请求次数 */
#define CSR_TILE_PPE_CSR_ENT_NUM_3_REG (CSR_TILE_PPE_CSR_BASE + 0x9C)            /* 匹配对应PPE程序入口地址的请求次数 */
#define CSR_TILE_PPE_CSR_ENT_NUM_4_REG (CSR_TILE_PPE_CSR_BASE + 0xA0)            /* 匹配对应PPE程序入口地址的请求次数 */
#define CSR_TILE_PPE_CSR_ENT_NUM_5_REG (CSR_TILE_PPE_CSR_BASE + 0xA4)            /* 匹配对应PPE程序入口地址的请求次数 */
#define CSR_TILE_PPE_CSR_ENT_NUM_6_REG (CSR_TILE_PPE_CSR_BASE + 0xA8)            /* 匹配对应PPE程序入口地址的请求次数 */
#define CSR_TILE_PPE_CSR_ENT_NUM_7_REG (CSR_TILE_PPE_CSR_BASE + 0xAC)            /* 匹配对应PPE程序入口地址的请求次数 */
#define CSR_TILE_PPE_CSR_EXIT_NUM_0_REG (CSR_TILE_PPE_CSR_BASE + 0xB0)           /* 匹配对应PPE程序出口地址的请求次数 */
#define CSR_TILE_PPE_CSR_EXIT_NUM_1_REG (CSR_TILE_PPE_CSR_BASE + 0xB4)           /* 匹配对应PPE程序出口地址的请求次数 */
#define CSR_TILE_PPE_CSR_EXIT_NUM_2_REG (CSR_TILE_PPE_CSR_BASE + 0xB8)           /* 匹配对应PPE程序出口地址的请求次数 */
#define CSR_TILE_PPE_CSR_EXIT_NUM_3_REG (CSR_TILE_PPE_CSR_BASE + 0xBC)           /* 匹配对应PPE程序出口地址的请求次数 */
#define CSR_TILE_PPE_CSR_EXIT_NUM_4_REG (CSR_TILE_PPE_CSR_BASE + 0xC0)           /* 匹配对应PPE程序出口地址的请求次数 */
#define CSR_TILE_PPE_CSR_EXIT_NUM_5_REG (CSR_TILE_PPE_CSR_BASE + 0xC4)           /* 匹配对应PPE程序出口地址的请求次数 */
#define CSR_TILE_PPE_CSR_EXIT_NUM_6_REG (CSR_TILE_PPE_CSR_BASE + 0xC8)           /* 匹配对应PPE程序出口地址的请求次数 */
#define CSR_TILE_PPE_CSR_EXIT_NUM_7_REG (CSR_TILE_PPE_CSR_BASE + 0xCC)           /* 匹配对应PPE程序出口地址的请求次数 */
#define CSR_TILE_PPE_CSR_PPE_PROG_EXE_TIME_REG (CSR_TILE_PPE_CSR_BASE + 0xD0)    /* PPE程序执行时间 */
#define CSR_TILE_PPE_CSR_PPE_PROG_EXE_LONG_REG (CSR_TILE_PPE_CSR_BASE + 0xD4)    /* PPE程序执行时间超长时的Engine状态 */
#define CSR_TILE_PPE_CSR_PPE_PROG_EXE_LONG_PW_REG \
    (CSR_TILE_PPE_CSR_BASE + 0xD8) /* PPE程序执行时间超长时的4个BR issue的PW_PTR */
#define CSR_TILE_PPE_CSR_PPE_PROG_EXE_LONG_MW_REG \
    (CSR_TILE_PPE_CSR_BASE + 0xDC) /* PPE程序执行时间超长时的4个BR issue的MW_PTR */
#define CSR_TILE_PPE_CSR_EXE_LONG_PW_REG_0_REG \
    (CSR_TILE_PPE_CSR_BASE + 0xE0) /* PPE程序执行时间超长时的4个BR issue的PW寄存器的值 */
#define CSR_TILE_PPE_CSR_EXE_LONG_PW_REG_1_REG \
    (CSR_TILE_PPE_CSR_BASE + 0xE4) /* PPE程序执行时间超长时的4个BR issue的PW寄存器的值 */
#define CSR_TILE_PPE_CSR_EXE_LONG_PW_REG_2_REG \
    (CSR_TILE_PPE_CSR_BASE + 0xE8) /* PPE程序执行时间超长时的4个BR issue的PW寄存器的值 */
#define CSR_TILE_PPE_CSR_EXE_LONG_PW_REG_3_REG \
    (CSR_TILE_PPE_CSR_BASE + 0xEC) /* PPE程序执行时间超长时的4个BR issue的PW寄存器的值 */
#define CSR_TILE_PPE_CSR_EXE_LONG_MW_REG_0_REG \
    (CSR_TILE_PPE_CSR_BASE + 0xF0) /* PPE程序执行时间超长时的4个BR issue的MW寄存器的值 */
#define CSR_TILE_PPE_CSR_EXE_LONG_MW_REG_1_REG \
    (CSR_TILE_PPE_CSR_BASE + 0xF4) /* PPE程序执行时间超长时的4个BR issue的MW寄存器的值 */
#define CSR_TILE_PPE_CSR_EXE_LONG_MW_REG_2_REG \
    (CSR_TILE_PPE_CSR_BASE + 0xF8) /* PPE程序执行时间超长时的4个BR issue的MW寄存器的值 */
#define CSR_TILE_PPE_CSR_EXE_LONG_MW_REG_3_REG \
    (CSR_TILE_PPE_CSR_BASE + 0xFC) /* PPE程序执行时间超长时的4个BR issue的MW寄存器的值 */

/* tile_qcm_csr Base address of Module's Register */
#define CSR_TILE_QCM_CSR_BASE (0x200)

/* **************************************************************************** */
/*                      tile_qcm_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_TILE_QCM_CSR_TILE_QCM_VERSION_REG (CSR_TILE_QCM_CSR_BASE + 0x0) /* Version Log register */
#define CSR_TILE_QCM_CSR_TILE_QCM_PERF_CNTL_REG \
    (CSR_TILE_QCM_CSR_BASE + 0x4) /* Quad core performance countrol register */
#define CSR_TILE_QCM_CSR_TILE_QCM_COMMON_CFG_REG (CSR_TILE_QCM_CSR_BASE + 0x8)    /* quad core global congfigure */
#define CSR_TILE_QCM_CSR_TILE_QCM_RESET_CFG_REG (CSR_TILE_QCM_CSR_BASE + 0xC)     /* quad core reset control */
#define CSR_TILE_QCM_CSR_TILE_QCM_C0_CSR_INT_REG (CSR_TILE_QCM_CSR_BASE + 0x10)   /* CSR interrupt to KISDON CORE */
#define CSR_TILE_QCM_CSR_TILE_QCM_C1_CSR_INT_REG (CSR_TILE_QCM_CSR_BASE + 0x14)   /* CSR interrupt to KISDON CORE */
#define CSR_TILE_QCM_CSR_TILE_QCM_C2_CSR_INT_REG (CSR_TILE_QCM_CSR_BASE + 0x18)   /* CSR interrupt to KISDON CORE */
#define CSR_TILE_QCM_CSR_TILE_QCM_C3_CSR_INT_REG (CSR_TILE_QCM_CSR_BASE + 0x1C)   /* CSR interrupt to KISDON CORE */
#define CSR_TILE_QCM_CSR_TILE_QCM_INT_VECTOR_REG (CSR_TILE_QCM_CSR_BASE + 0x20)   /* interrupt vector */
#define CSR_TILE_QCM_CSR_TILE_QCM_INT_REG (CSR_TILE_QCM_CSR_BASE + 0x24)          /* interrupt data */
#define CSR_TILE_QCM_CSR_TILE_QCM_INT_MASK_REG (CSR_TILE_QCM_CSR_BASE + 0x28)     /* interrupt mask */
#define CSR_TILE_QCM_CSR_TILE_QCM_C0_SPRAM_ERR_REG (CSR_TILE_QCM_CSR_BASE + 0x2C) /* KISDON core 0 spram error */
#define CSR_TILE_QCM_CSR_TILE_QCM_C1_SPRAM_ERR_REG (CSR_TILE_QCM_CSR_BASE + 0x30) /* KISDON core 1 spram error */
#define CSR_TILE_QCM_CSR_TILE_QCM_C2_SPRAM_ERR_REG (CSR_TILE_QCM_CSR_BASE + 0x34) /* KISDON core 2 spram error */
#define CSR_TILE_QCM_CSR_TILE_QCM_C3_SPRAM_ERR_REG (CSR_TILE_QCM_CSR_BASE + 0x38) /* KISDON core 3 spram error */
#define CSR_TILE_QCM_CSR_C0_LSUL2_CSR_CACHE_ADDR_ERR_REG \
    (CSR_TILE_QCM_CSR_BASE + 0x3C) /* KISDON core 0 LSUL2 cache address error */
#define CSR_TILE_QCM_CSR_C1_LSUL2_CSR_CACHE_ADDR_ERR_REG \
    (CSR_TILE_QCM_CSR_BASE + 0x40) /* KISDON core 1 LSUL2 cache address error */
#define CSR_TILE_QCM_CSR_C2_LSUL2_CSR_CACHE_ADDR_ERR_REG \
    (CSR_TILE_QCM_CSR_BASE + 0x44) /* KISDON core 2 LSUL2 cache address error */
#define CSR_TILE_QCM_CSR_C3_LSUL2_CSR_CACHE_ADDR_ERR_REG \
    (CSR_TILE_QCM_CSR_BASE + 0x48) /* KISDON core 3 LSUL2 cache address error */
#define CSR_TILE_QCM_CSR_TILE_QCM_LSU_ERR_REG (CSR_TILE_QCM_CSR_BASE + 0x4C) /* LSU Interface error register */
#define CSR_TILE_QCM_CSR_TILE_QCM_LSU_ERR_MASK_REG \
    (CSR_TILE_QCM_CSR_BASE + 0x50)                                             /* LSU Interface error register mask */
#define CSR_TILE_QCM_CSR_RESERVD_REG (CSR_TILE_QCM_CSR_BASE + 0x54)            /* RESERVD */
#define CSR_TILE_QCM_CSR_TILE_QCM_PERF_CNT0_REG (CSR_TILE_QCM_CSR_BASE + 0x58) /* performance counter */
#define CSR_TILE_QCM_CSR_TILE_QCM_PERF_CNT1_REG (CSR_TILE_QCM_CSR_BASE + 0x60) /* performance counter */
#define CSR_TILE_QCM_CSR_TILE_QCM_PERF_CNT2_REG (CSR_TILE_QCM_CSR_BASE + 0x68) /* performance counter */
#define CSR_TILE_QCM_CSR_TILE_QCM_CLR_G_FLAG_REG \
    (CSR_TILE_QCM_CSR_BASE + 0x70) /* control register to clear the G flag in QMC/ICRC, after l2i time out */
#define CSR_TILE_QCM_CSR_TILE_QCM_MON_CFG_REG (CSR_TILE_QCM_CSR_BASE + 0x74)            /* monitor control */
#define CSR_TILE_QCM_CSR_TILE_QCM_MON_STA_REG (CSR_TILE_QCM_CSR_BASE + 0x78)            /* monitor status */
#define CSR_TILE_QCM_CSR_TILE_QCM_OSD_STA_REG (CSR_TILE_QCM_CSR_BASE + 0x80)            /* QCM CORE oustanding status */
#define CSR_TILE_QCM_CSR_TILE_QCM_SRC_OEID_REG (CSR_TILE_QCM_CSR_BASE + 0x84)           /* OEID and SRC_TAG_L */
#define CSR_TILE_QCM_CSR_TILE_QCM_MMU_ADDR0_REG (CSR_TILE_QCM_CSR_BASE + 0x88)          /* mmu address0 config */
#define CSR_TILE_QCM_CSR_TILE_QCM_MMU_ADDR1_REG (CSR_TILE_QCM_CSR_BASE + 0x8C)          /* mmu address1 config */
#define CSR_TILE_QCM_CSR_TILE_QCM_MMU_ADDR2_REG (CSR_TILE_QCM_CSR_BASE + 0x90)          /* mmu address2 config */
#define CSR_TILE_QCM_CSR_TILE_QCM_SPRAM_ECC_ERR_REG (CSR_TILE_QCM_CSR_BASE + 0x94)      /* SPRAM ECC ERROR */
#define CSR_TILE_QCM_CSR_TILE_QCM_SPRAM_ECC_ERR_MASK_REG (CSR_TILE_QCM_CSR_BASE + 0x98) /* SPRAM ECC ERROR mask */

/* tile_tiu_csr Base address of Module's Register */
#define CSR_TILE_TIU_CSR_BASE (0x0)

/* **************************************************************************** */
/*                      tile_tiu_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_TILE_TIU_CSR_TILE_TIU_VERSION_REG (CSR_TILE_TIU_CSR_BASE + 0x0) /* Version Log register */
#define CSR_TILE_TIU_CSR_TILE_TIU_COMMON_CFG_REG                                                                       \
    (CSR_TILE_TIU_CSR_BASE + 0x4) /* This config is used to set a the values   that RING interfaces can make a request \
                                     to MTC when the fullness of RING interface buffer reach to this value. */
#define CSR_TILE_TIU_CSR_RING_RX_CORRECT_API_CNT_REG \
    (CSR_TILE_TIU_CSR_BASE + 0x8) /* The number of correct api received in RING interfaces */
#define CSR_TILE_TIU_CSR_RING_RX_ERR_API_CNT_REG \
    (CSR_TILE_TIU_CSR_BASE + 0xC) /* The number of error api received in RING interfaces */
#define CSR_TILE_TIU_CSR_RING_RX_DROP_FLIT_CNT_REG \
    (CSR_TILE_TIU_CSR_BASE + 0x10) /* The number of dropped flits received in RING interfaces */
#define CSR_TILE_TIU_CSR_SMF_RX_CORRECT_API_CNT_REG \
    (CSR_TILE_TIU_CSR_BASE + 0x14) /* The number of correct api received in SMF interfaces */
#define CSR_TILE_TIU_CSR_SMF_RX_ERR_API_CNT_REG \
    (CSR_TILE_TIU_CSR_BASE + 0x18) /* The number of error api received in SMF interfaces */
#define CSR_TILE_TIU_CSR_SMF_RX_DROP_FLIT_CNT_REG \
    (CSR_TILE_TIU_CSR_BASE + 0x1C) /* The number of dropped flits received in SMF interfaces */
#define CSR_TILE_TIU_CSR_CAL_RX_CORRECT_API_CNT_REG \
    (CSR_TILE_TIU_CSR_BASE + 0x20) /* The number of correct api received in CAL interfaces */
#define CSR_TILE_TIU_CSR_CAL_RX_ERR_API_CNT_REG \
    (CSR_TILE_TIU_CSR_BASE + 0x24) /* The number of error api received in CAL interfaces */
#define CSR_TILE_TIU_CSR_CAL_RX_DROP_FLIT_CNT_REG \
    (CSR_TILE_TIU_CSR_BASE + 0x28) /* The number of dropped flits received in CAL interfaces */
#define CSR_TILE_TIU_CSR_QU_RX_CORRECT_API_CNT_REG \
    (CSR_TILE_TIU_CSR_BASE + 0x2C) /* The number of correct api received in QU interfaces */
#define CSR_TILE_TIU_CSR_QU_RX_ERR_API_CNT_REG \
    (CSR_TILE_TIU_CSR_BASE + 0x30) /* The number of error api received in QU interfaces */
#define CSR_TILE_TIU_CSR_QU_RX_DROP_FLIT_CNT_REG \
    (CSR_TILE_TIU_CSR_BASE + 0x34) /* The number of dropped flits received in QU interfaces */
#define CSR_TILE_TIU_CSR_CPB_RX_CORRECT_API_CNT_REG \
    (CSR_TILE_TIU_CSR_BASE + 0x38) /* The number of correct api received in CPB interfaces */
#define CSR_TILE_TIU_CSR_CPB_RX_ERR_API_CNT_REG \
    (CSR_TILE_TIU_CSR_BASE + 0x3C) /* The number of error api received in CPB interfaces */
#define CSR_TILE_TIU_CSR_CPB_RX_DROP_FLIT_CNT_REG \
    (CSR_TILE_TIU_CSR_BASE + 0x40) /* The number of dropped flits received in CPB interfaces */
#define CSR_TILE_TIU_CSR_TIU_INT_VECTOR_REG (CSR_TILE_TIU_CSR_BASE + 0x44)
#define CSR_TILE_TIU_CSR_TIU_INT_REG (CSR_TILE_TIU_CSR_BASE + 0x48)      /* SMIR interrupt data */
#define CSR_TILE_TIU_CSR_TIU_INT_MASK_REG (CSR_TILE_TIU_CSR_BASE + 0x4C) /* SMIR interrupt mask configuration */
#define CSR_TILE_TIU_CSR_RING_ITF_ERR_REG (CSR_TILE_TIU_CSR_BASE + 0x50)
#define CSR_TILE_TIU_CSR_RING_ITF_ERR_MASK_REG (CSR_TILE_TIU_CSR_BASE + 0x54)
#define CSR_TILE_TIU_CSR_SMF_ITF_ERR_REG (CSR_TILE_TIU_CSR_BASE + 0x58)
#define CSR_TILE_TIU_CSR_SMF_ITF_ERR_MASK_REG (CSR_TILE_TIU_CSR_BASE + 0x5C)
#define CSR_TILE_TIU_CSR_CAL_ITF_ERR_REG (CSR_TILE_TIU_CSR_BASE + 0x60)
#define CSR_TILE_TIU_CSR_CAL_ITF_ERR_MASK_REG (CSR_TILE_TIU_CSR_BASE + 0x64)
#define CSR_TILE_TIU_CSR_QU_ITF_ERR_REG (CSR_TILE_TIU_CSR_BASE + 0x68)
#define CSR_TILE_TIU_CSR_QU_ITF_ERR_MASK_REG (CSR_TILE_TIU_CSR_BASE + 0x6C)
#define CSR_TILE_TIU_CSR_CPB_ITF_ERR_REG (CSR_TILE_TIU_CSR_BASE + 0x70)
#define CSR_TILE_TIU_CSR_CPB_ITF_ERR_MASK_REG (CSR_TILE_TIU_CSR_BASE + 0x74)
#define CSR_TILE_TIU_CSR_RING_RQST_CHNL_ERR_REG (CSR_TILE_TIU_CSR_BASE + 0x78)
#define CSR_TILE_TIU_CSR_TIU_INDRECT_CTRL_REG (CSR_TILE_TIU_CSR_BASE + 0x80)    /* indirect access address registers */
#define CSR_TILE_TIU_CSR_TIU_INDRECT_TIMEOUT_REG (CSR_TILE_TIU_CSR_BASE + 0x84) /* memory access timeout configure */
#define CSR_TILE_TIU_CSR_TIU_INDRECT_DATA0_REG (CSR_TILE_TIU_CSR_BASE + 0x88)   /* indirect access data registers */
#define CSR_TILE_TIU_CSR_TIU_INDRECT_DATA1_REG (CSR_TILE_TIU_CSR_BASE + 0x8C)   /* indirect access data registers */
#define CSR_TILE_TIU_CSR_TIU_INDRECT_DATA2_REG (CSR_TILE_TIU_CSR_BASE + 0x90)   /* indirect access data registers */
#define CSR_TILE_TIU_CSR_CPB_SCAT_ECC_1BIT_ERR_REG \
    (CSR_TILE_TIU_CSR_BASE + 0xA0) /* ECC 1 bit error occurs in cpb scatter table memory */
#define CSR_TILE_TIU_CSR_CPB_SCAT_ECC_2BIT_ERR_REG \
    (CSR_TILE_TIU_CSR_BASE + 0xA4) /* ECC 2 bit error occurs in cpb scatter table memory */
#define CSR_TILE_TIU_CSR_TILE_TIU_COMMON_CFG1_REG \
    (CSR_TILE_TIU_CSR_BASE + 0xB0) /* This config is used to hardware issue some API */
#define CSR_TILE_TIU_CSR_TILE_TIU_COMMON_CFG2_REG \
    (CSR_TILE_TIU_CSR_BASE + 0xB4) /* This config is used to hardware issue some API */
#define CSR_TILE_TIU_CSR_TILE_TIU_COMMON_CFG3_REG \
    (CSR_TILE_TIU_CSR_BASE + 0xB8) /* This config is used to hardware issue some API */
#define CSR_TILE_TIU_CSR_TILE_TIU_COMMON_CFG4_REG \
    (CSR_TILE_TIU_CSR_BASE + 0xBC) /* This config is used to hardware issue some API */
#define CSR_TILE_TIU_CSR_TILE_TIU_COMMON_CFG5_REG \
    (CSR_TILE_TIU_CSR_BASE + 0xC0) /* This config is used to hardware issue some API */
#define CSR_TILE_TIU_CSR_TILE_TIU_SCAT_CFG0_REG (CSR_TILE_TIU_CSR_BASE + 0xC4) /* This config is used for scatter */
#define CSR_TILE_TIU_CSR_TILE_TIU_SCAT_CFG1_REG (CSR_TILE_TIU_CSR_BASE + 0xC8) /* This config is used for scatter */
#define CSR_TILE_TIU_CSR_QCM10_TH_HQ_EOP_ST_REG (CSR_TILE_TIU_CSR_BASE + 0xD0) /* TIU HIA状态0 */
#define CSR_TILE_TIU_CSR_QCM32_TH_HQ_EOP_ST_REG (CSR_TILE_TIU_CSR_BASE + 0xD4) /* TIU HIA状态1 */
#define CSR_TILE_TIU_CSR_QCM54_TH_HQ_EOP_ST_REG (CSR_TILE_TIU_CSR_BASE + 0xD8) /* TIU HIA状态2 */
#define CSR_TILE_TIU_CSR_TIU_FIFO_ST_REG (CSR_TILE_TIU_CSR_BASE + 0xDC)        /* TIU HIA状态3 */
#define CSR_TILE_TIU_CSR_TIU_HIA_ERR_REG (CSR_TILE_TIU_CSR_BASE + 0xE0)        /* TIU HIA错误 */
#define CSR_TILE_TIU_CSR_C2R_FIFO_OV_REG (CSR_TILE_TIU_CSR_BASE + 0xE4)        /* C2R FIFO溢出 */
#define CSR_TILE_TIU_CSR_Q2R_FIFO_OV_REG (CSR_TILE_TIU_CSR_BASE + 0xE8)        /* Q2R FIFO溢出 */
#define CSR_TILE_TIU_CSR_C2R_FIFO_1BIT_ERR_REG \
    (CSR_TILE_TIU_CSR_BASE + 0xEC) /* ECC 1 bit error occurs in HIA C2R FIFO memory */
#define CSR_TILE_TIU_CSR_C2R_FIFO_2BIT_ERR_REG \
    (CSR_TILE_TIU_CSR_BASE + 0xF0) /* ECC 2 bit error occurs in HIA C2R FIFO memory */
#define CSR_TILE_TIU_CSR_Q2R_FIFO_1BIT_ERR_REG \
    (CSR_TILE_TIU_CSR_BASE + 0xF4) /* ECC 1 bit error occurs in HIA Q2R FIFO memory */
#define CSR_TILE_TIU_CSR_Q2R_FIFO_2BIT_ERR_REG \
    (CSR_TILE_TIU_CSR_BASE + 0xF8) /* ECC 2 bit error occurs in HIA Q2R FIFO memory */

/* tile_tou_csr Base address of Module's Register */
#define CSR_TILE_TOU_CSR_BASE (0xE00)

/* **************************************************************************** */
/*                      tile_tou_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_TILE_TOU_CSR_TILE_TOU_VERSION_REG (CSR_TILE_TOU_CSR_BASE + 0x0)    /* Version Log register */
#define CSR_TILE_TOU_CSR_TILE_EXCEPTION_BASE_REG (CSR_TILE_TOU_CSR_BASE + 0x4) /* Exception base address */
#define CSR_TILE_TOU_CSR_TILE_TOU_COMMON_CFG_REG                                                                       \
    (CSR_TILE_TOU_CSR_BASE + 0x8) /* This config is used to set a the values   that RING interfaces can make a request \
                                     to MTC when the fullness of RING interface buffer reach to this value. */
#define CSR_TILE_TOU_CSR_RING_REQ_CORRECT_API_CNT_REG \
    (CSR_TILE_TOU_CSR_BASE + 0xC) /* The number of correct api sent from RING interfaces */
#define CSR_TILE_TOU_CSR_RING_REQ_ERR_API_CNT_REG \
    (CSR_TILE_TOU_CSR_BASE + 0x10) /* The number of error api sent from RING interfaces */
#define CSR_TILE_TOU_CSR_RING_RESP_CORRECT_API_CNT_REG \
    (CSR_TILE_TOU_CSR_BASE + 0x14) /* The number of correct api sent from RING response interfaces */
#define CSR_TILE_TOU_CSR_RING_RESP_ERR_API_CNT_REG \
    (CSR_TILE_TOU_CSR_BASE + 0x18) /* The number of error api sent from RING response interfaces */
#define CSR_TILE_TOU_CSR_SMF_CORRECT_API_CNT_REG \
    (CSR_TILE_TOU_CSR_BASE + 0x1C) /* The number of correct api sent from SMF interfaces */
#define CSR_TILE_TOU_CSR_SMF_ERR_API_CNT_REG \
    (CSR_TILE_TOU_CSR_BASE + 0x20) /* The number of error api sent from SMF interfaces */
#define CSR_TILE_TOU_CSR_QU_CORRECT_API_CNT_REG \
    (CSR_TILE_TOU_CSR_BASE + 0x24) /* The number of correct api sent from QU interfaces */
#define CSR_TILE_TOU_CSR_QU_ERR_API_CNT_REG \
    (CSR_TILE_TOU_CSR_BASE + 0x28) /* The number of error api sent from QU interfaces */
#define CSR_TILE_TOU_CSR_CPB_CORRECT_API_CNT_REG \
    (CSR_TILE_TOU_CSR_BASE + 0x2C) /* The number of correct api sent from CPB interfaces */
#define CSR_TILE_TOU_CSR_CPB_ERR_API_CNT_REG \
    (CSR_TILE_TOU_CSR_BASE + 0x30) /* The number of error api sent from CPB interfaces */
#define CSR_TILE_TOU_CSR_TOU_INT_VECTOR_REG (CSR_TILE_TOU_CSR_BASE + 0x34)
#define CSR_TILE_TOU_CSR_TOU_INT_REG (CSR_TILE_TOU_CSR_BASE + 0x38)      /* TOU interrupt data */
#define CSR_TILE_TOU_CSR_TOU_INT_MASK_REG (CSR_TILE_TOU_CSR_BASE + 0x3C) /* TOU interrupt mask configuration */
#define CSR_TILE_TOU_CSR_PRB_ECC_1BIT_ERR_REG \
    (CSR_TILE_TOU_CSR_BASE + 0x40) /* ECC 1 bit error occurs in the PRB memory */
#define CSR_TILE_TOU_CSR_PRBN_ECC_1BIT_ERR_REG \
    (CSR_TILE_TOU_CSR_BASE + 0x44) /* ECC 1 bit error occurs in the PRBN(non RING)memory */
#define CSR_TILE_TOU_CSR_PRB_ECC_2BIT_ERR_REG \
    (CSR_TILE_TOU_CSR_BASE + 0x48) /* ECC 2 bit error occurs in the PRB memory */
#define CSR_TILE_TOU_CSR_PRBN_ECC_2BIT_ERR_REG \
    (CSR_TILE_TOU_CSR_BASE + 0x4C) /* ECC 2 bit error occurs in the PRBN memory */
#define CSR_TILE_TOU_CSR_TILE_TOU_WEIGHT_CFG_REG \
    (CSR_TILE_TOU_CSR_BASE + 0x50) /* TOU prb/prbn stage 2 WRR weight configure */
#define CSR_TILE_TOU_CSR_TILE_TOU_PRB_STAT_REG (CSR_TILE_TOU_CSR_BASE + 0x54)      /* TOU PRB/PRBN 资源 */
#define CSR_TILE_TOU_CSR_TILE_TOU_RING_ARB_REQ_REG (CSR_TILE_TOU_CSR_BASE + 0x58)  /* TOU RING pipeline 请求 */
#define CSR_TILE_TOU_CSR_TILE_TOU_NRING_ARB_REQ_REG (CSR_TILE_TOU_CSR_BASE + 0x5C) /* TOU non RING pipeline 请求 */
#define CSR_TILE_TOU_CSR_TILE_TOU_CRDT_CFG_REG \
    (CSR_TILE_TOU_CSR_BASE + 0x60) /* 选择RING pipeline和non-RING pipeline各个VC的credit counter */
#define CSR_TILE_TOU_CSR_TILE_TOU_RING_CRDT_REG                                                                      \
    (CSR_TILE_TOU_CSR_BASE + 0x64) /* 当前选中的credit counter，配置来自TILE_TOU_CRDT_CFG的rp_tile_tou_ring_crdt_sel \
                                    */
#define CSR_TILE_TOU_CSR_TILE_TOU_NRING_CRDT_REG                                                                      \
    (CSR_TILE_TOU_CSR_BASE + 0x68) /* 当前选中的credit counter，配置来自TILE_TOU_CRDT_CFG的rp_tile_tou_nring_crdt_sel \
                                    */
#define CSR_TILE_TOU_CSR_TILE_TOU_L2I_API_CNT_REG (CSR_TILE_TOU_CSR_BASE + 0x6C)    /* L2I refill的指令数 */
#define CSR_TILE_TOU_CSR_TILE_TOU_THRSL_CNT_REG (CSR_TILE_TOU_CSR_BASE + 0x70)      /* TILE release thread 个数 */
#define CSR_TILE_TOU_CSR_TILE_TOU_QCM_RST_REQ_REG (CSR_TILE_TOU_CSR_BASE + 0x74)    /* 每个QCM的单独软复位请求 */
#define CSR_TILE_TOU_CSR_TILE_TOU_VC_TIMEOUT_CFG_REG (CSR_TILE_TOU_CSR_BASE + 0x78) /* VC等待仲裁超时设置 */
#define CSR_TILE_TOU_CSR_TILE_TOU_RING_REQ_VC_TIMEOUT_CNT_REG \
    (CSR_TILE_TOU_CSR_BASE + 0x7C) /* RING通道进入VC超时仲裁模式的次数 */
#define CSR_TILE_TOU_CSR_TILE_TOU_QU_VC_TIMEOUT_CNT_REG \
    (CSR_TILE_TOU_CSR_BASE + 0x80) /* QU通道进入VC超时仲裁模式的次数 */
#define CSR_TILE_TOU_CSR_TILE_TOU_CPB_VC_TIMEOUT_CNT_REG \
    (CSR_TILE_TOU_CSR_BASE + 0x84)                                              /* CPB通道进入VC超时仲裁模式的次数 */
#define CSR_TILE_TOU_CSR_TOU_INDRECT_CTRL_REG (CSR_TILE_TOU_CSR_BASE + 0x90)    /* indirect access address registers */
#define CSR_TILE_TOU_CSR_TOU_INDRECT_TIMEOUT_REG (CSR_TILE_TOU_CSR_BASE + 0x94) /* memory access timeout configure */
#define CSR_TILE_TOU_CSR_TOU_INDRECT_DATA0_REG (CSR_TILE_TOU_CSR_BASE + 0x98)   /* indirect access data registers */
#define CSR_TILE_TOU_CSR_TOU_INDRECT_DATA1_REG (CSR_TILE_TOU_CSR_BASE + 0x9C)   /* indirect access data registers */
#define CSR_TILE_TOU_CSR_TOU_INDRECT_DATA2_REG (CSR_TILE_TOU_CSR_BASE + 0xA0)   /* indirect access data registers */
#define CSR_TILE_TOU_CSR_TOU_INDRECT_DATA3_REG (CSR_TILE_TOU_CSR_BASE + 0xA4)   /* indirect access data registers */
#define CSR_TILE_TOU_CSR_TOU_INDRECT_DATA4_REG (CSR_TILE_TOU_CSR_BASE + 0xA8)   /* indirect access data registers */
#define CSR_TILE_TOU_CSR_TOU_INDRECT_DATA5_REG (CSR_TILE_TOU_CSR_BASE + 0xAC)   /* indirect access data registers */
#define CSR_TILE_TOU_CSR_RING_MEM_ECC_1BIT_ERR_REG \
    (CSR_TILE_TOU_CSR_BASE + 0xB0) /* ECC 1 bit error occurs in ring merge table memory */
#define CSR_TILE_TOU_CSR_RING_MEM_ECC_2BIT_ERR_REG \
    (CSR_TILE_TOU_CSR_BASE + 0xB4) /* ECC 2 bit error occurs in ring merge table memory */
#define CSR_TILE_TOU_CSR_CPB_MEM_ECC_1BIT_ERR_REG \
    (CSR_TILE_TOU_CSR_BASE + 0xB8) /* ECC 1 bit error occurs in cpb merge table memory */
#define CSR_TILE_TOU_CSR_CPB_MEM_ECC_2BIT_ERR_REG \
    (CSR_TILE_TOU_CSR_BASE + 0xBC) /* ECC 2 bit error occurs in cpb merge table memory */
#define CSR_TILE_TOU_CSR_QPC_MEM_ECC_1BIT_ERR_REG \
    (CSR_TILE_TOU_CSR_BASE + 0xC0) /* ECC 1 bit error occurs in qpc merge table memory */
#define CSR_TILE_TOU_CSR_QPC_MEM_ECC_2BIT_ERR_REG \
    (CSR_TILE_TOU_CSR_BASE + 0xC4) /* ECC 2 bit error occurs in qpc merge table memory */
#define CSR_TILE_TOU_CSR_TILE_TOU_NEW_CFG_REG (CSR_TILE_TOU_CSR_BASE + 0xD0) /* TOU config */
#define CSR_TILE_TOU_CSR_QUF_ND2RS_FIFO_1BIT_ERR_REG \
    (CSR_TILE_TOU_CSR_BASE + 0xD4) /* ECC 1 bit error occurs in QUF_ND2RS FIFO memory */
#define CSR_TILE_TOU_CSR_QUF_ND2RS_FIFO_2BIT_ERR_REG \
    (CSR_TILE_TOU_CSR_BASE + 0xD8) /* ECC 2 bit error occurs in QUF_ND2RS FIFO memory */
#define CSR_TILE_TOU_CSR_SMF_ND2RS_FIFO_1BIT_ERR_REG \
    (CSR_TILE_TOU_CSR_BASE + 0xDC) /* ECC 1 bit error occurs in SMF_ND2RS FIFO memory */
#define CSR_TILE_TOU_CSR_SMF_ND2RS_FIFO_2BIT_ERR_REG \
    (CSR_TILE_TOU_CSR_BASE + 0xE0) /* ECC 2 bit error occurs in SMF_ND2RS FIFO memory */
#define CSR_TILE_TOU_CSR_QUF_ND2RS_FIFO_OVF_REG (CSR_TILE_TOU_CSR_BASE + 0xE4) /* FIFO溢出 */
#define CSR_TILE_TOU_CSR_SMF_ND2RS_FIFO_OVF_REG (CSR_TILE_TOU_CSR_BASE + 0xE8) /* FIFO溢出 */
#define CSR_TILE_TOU_CSR_QPCI_ND2RS_FIFO_ST_REG (CSR_TILE_TOU_CSR_BASE + 0xEC) /* QPC接口FIFO状态 */
#define CSR_TILE_TOU_CSR_TOU_MON_CFG_REG (CSR_TILE_TOU_CSR_BASE + 0xF0)        /* Monitor相关配置 */
#define CSR_TILE_TOU_CSR_TOU_MON_CNT_REG (CSR_TILE_TOU_CSR_BASE + 0xF4)        /* Monitor统计计数器 */
#define CSR_TILE_TOU_CSR_TOU_JTAG_EN_REG (CSR_TILE_TOU_CSR_BASE + 0xF8)        /* JTAG 配置使能 */

#endif // SD5860_SD5860_ADDR_DEFINE_H
